| Publication Type |
Journal Article |
| School or College |
College of Engineering |
| Department |
Computing, School of |
| Creator |
Davis, Alan L. |
| Other Author |
Weiser, Uri |
| Title |
Mathematical representation for VLSI arrays |
| Date |
1980 |
| Description |
This paper introduces a methodology for mapping algorithmic description into a concurrent implementation on silicon. This methodology can help in the solution of important problems using a new technique for the representation of highly parallel networks. This new approach for the representation of computational networks was inspired by the systolic array approach [H. T. Kung & Leiserson 78], and by the linear approach to computational networks [Cohen 78]. It creates tools which will enable the creation of new high performance implementations as well as verification tools. This approach is more complex than the linear approach [Gill 66, Cohen 78]. but can also be used to verify computation networks. |
| Type |
Text |
| Publisher |
University of Utah |
| First Page |
1 |
| Last Page |
28 |
| Subject |
VLSI arrays |
| Subject LCSH |
Integrated circuits -- Very large scale integration |
| Language |
eng |
| Bibliographic Citation |
Weiser, U., & Davis, Alan L. (1980). Mathematical representation for VLSI arrays. 1-28. UUCS-80-111. |
| Series |
University of Utah Computer Science Technical Report |
| Relation is Part of |
ARPANET |
| Rights Management |
©University of Utah |
| Format Medium |
application/pdf |
| Format Extent |
13,366,596 bytes |
| Identifier |
ir-main,16132 |
| ARK |
ark:/87278/s6v702qx |
| Setname |
ir_uspace |
| ID |
702642 |
| Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6v702qx |
