| Publication Type |
Journal Article |
| School or College |
College of Engineering |
| Department |
Computing, School of |
| Creator |
Gerpheide, George E. |
| Title |
Bit-driven logic: a style of digital logic for VLSI design |
| Date |
1980 |
| Description |
This memo describes a new style of low-level digital logic design called Bit-Driven Logic (BDL) which may prove attractive for the design of VLSI chips. BDL is an application of speed-independent, data-flow ideas to a very low level. It has the advantages of good locality, clockless operation, and inherent pipelining leading to high through put. The G-Net, a graph model similar to the Petri Net, is presented to represent BDL circuits and the through put of acyclic G-Nets is investigated. The concepts of skew and thickness, and the use of shims as well as drawings in Time Normal Form, are presented to enable acyclic G-Nets to be designed which support maximum through put. The suitability of uniform-array concepts for VLSI implementation, particularly the SLA, is shown by means of examples, the most involved of which is an iterative array multiplier. |
| Type |
Text |
| Publisher |
University of Utah |
| First Page |
1 |
| Last Page |
40 |
| Subject |
Bit-Driven Logic; BDL; Digital logic design; VLSI chips |
| Subject LCSH |
Integrated circuits -- Very large scale integration |
| Language |
eng |
| Bibliographic Citation |
Gerpheide, G. E. (1980). Bit-driven logic: a style of digital logic for VLSI design. 1-40. UCCS-80-113. |
| Series |
University of Utah Computer Science Technical Report |
| Rights Management |
©University of Utah |
| Format Medium |
application/pdf |
| Format Extent |
18,050,307 bytes |
| Identifier |
ir-main,16134 |
| ARK |
ark:/87278/s65m6q5g |
| Setname |
ir_uspace |
| ID |
705122 |
| Reference URL |
https://collections.lib.utah.edu/ark:/87278/s65m6q5g |
